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complete, high resolution 16-bit a/d converter adadc71 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features 16-bit converter with reference and clock 0.003% maximum nonlinearity no missing codes to 14 bits fast conversion: 35 s (14 bit) short cycle capability parallel logic outputs low power: 645 mw typical industry standard pinout applications medical and analytic instrumentation precision measurement for industrial robots automatic test equipment multi-channel data acquisition systems servo-control systems functional block diagram 03537-001 (msb) bit 1 1 bit 2 2 bit 3 3 bit 4 4 bit 5 5 bit 6 6 bit 7 7 bit 8 8 bit 9 9 bit 10 10 bit 11 11 bit 12 12 (lsb for 13 bits) bit 13 13 (lsb for 14 bits) bit 14 14 bit 15 15 bit 16 16 short cycle 32 convert command 31 +5v dc supply v l 30 gain adjust 29 +15v dc supply v cc 28 comparator in 27 bipolar offset 26 +10v 25 +20v 24 ref out (4.3v) 23 analog common 22 ?15v dc supply v ee 21 clock out 20 digital common 19 status 18 nc nc = no connect 17 16-bit dac 16-bit sar clock reference comparator 7.5k 3.75k 3.75k adadc71 figure 1. general description the adadc71 is a high resolution 16-bit hybrid ic analog-to- digital converter including reference, clock, and laser-trimmed thin-film components. the package is a compact 32-pin hermetic ceramic dip. the thin-film scaling resistors allow analog input ranges of 2.5 v, 5 v, 10 v, 0 to +5 v, 0 to +10 v, and 0 to +20 v. important performance characteristics of the device are maximum linearity error of 0.003% of fsr, and maximum conversion time of 50 s. this performance is due to innovative design and the use of proprietary monolithic dac chips. laser- trimmed thin-film resistors provide the linearity and wide temperature range for no missing codes. the adadc71 provides data in parallel format with corresponding clock and status outputs. all digital inputs and outputs are ttl-compatible. the adadc71 used to provide data in a serial format. the serial output function is no longer available after date code 0120. product highlights 1. the adadc71 provides 16-bit resolution with a maximum linearity error less than 0.003% (0.006% for j grades) at 25 o c. 2. conversion time is 35 s typical (50 s max) to 14 bits with short cycle capability. 3. two binary codes are available on the adadc71 output: complementary straight binary (csb) for unipolar input voltage ranges, and complementary offset binary (cob) for bipolar input ranges. complementary twos complement (ctc) coding may be obtained by inverting pin 1 (msb). 4. the proprietary chips used in this hybrid design provide excellent stability over temperature, and lower chip count for improved reliability.
adadc71 rev. c | page 2 of 12 table of contents specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 theory of operation ........................................................................ 6 description of operation ................................................................ 7 gain adjustment .......................................................................... 7 zero offset adjustment ............................................................... 7 timing ............................................................................................ 7 digital output data ......................................................................8 input scaling ..................................................................................8 calibration (14-bit resolution examples) .................................9 grounding, decoupling, and layout considerations ........... 10 t/h requirements for high resolution applications .......... 10 using the adadc71 at slower conversion times ............... 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 6/05rev. b to rev. c updated format..................................................................universal removed adadc72..........................................................universal updated outline dimensions ....................................................... 12 changes to ordering guide .......................................................... 12
adadc71 rev. c | page 3 of 12 specifications typical at t a = + 25 o c, v s = 15 v, +5 v unless otherwise noted. table 1. araeter in typ a nits coent resolution 16 bits analog inputs voltage ranges bipolar 2.5 v 5 v 10 v unipolar 0 to +5 v 0 to +10 v 0 to +20 v impedance (direct input) 0 to 5 v, 2.5 v 1.88 k 0 to 10 v, 5.0 v 3.75 k 0 to 20 v, 10 v 7.50 k digital inputs 1 convert command trailing edge of positive 50 ns (min) pulse initiates conversion logic loading 1 lsttl load transfer characteristics accuracy gain error 0.1 2 0.2 % offset error unipolar 0.05 2 0.1 % of fsr 3 bipolar 0.1 2 0.2 % of fsr linearity error 0.006 % of fsr j grade 0.003 % of fsr k grade inherent quantization error 1/2 lsb differential linearity error 0.003 % of fsr no missing codes @ 25 o c 4 to 14 bits guaranteed k grade power supply sensitivity 15 v dc 0.003 % of fsr/%v s +5 v dc 0.001 % of fsr/%v s conversion time 5 (14 bits) 35 50 s warm-up time 5 minutes drift gain 15 ppm/ o c offset unipolar 2 4 ppm of fsr/ o c bipolar 10 ppm of fsr/ o c linearity 2 3 ppm of fsr/ o c guaranteed no missing code temperature range 4 0 to 70 o c jd (13 bits), kd (14 bits)
adadc71 rev. c | page 4 of 12 parameter min typ max units comment digital output 1 all codes complementary parallel output codes 6 unipolar csb bipolar cob, ctc 7 output drive 5 lsttl loads status logic 1 during conversion status output drive 5 lsttl loads internal clock clock output drive 5 lsttl loads frequency 400 khz internal reference voltage 6.3 v dc error 5 % max external current drain with no degradation of specifications 200 a temperature coefficient 10 ppm/ o c power supply requirements power consumption 645 850 mw rated voltage, analog 15 0.5 v dc rated voltage, digital 5 0.25 v dc supply drain +15 v dc +16 ma supply drain ?15 v dc ?21 ma supply drain +5 v dc +18 ma temperature range specification 0 to +70 c operating (derated specs) ?25 to +85 c storage ?55 to +125 c 1 for inputs logic 0 = 0.8 v, max. logic 1 = 2.0 v, min. fo r digital outputs logic 0 = 0.4 v max. logic 1 = 2.4 v min. 2 adjustable to 0. 3 full scale range. 4 for definition of no missing codes, refer to the th eory of operation section. 5 conversion time may be shortened with short cycle set for lower resolution. 6 csbcomplementary straight binary. cob complementa ry offset binary, ctccomple mentary twos complement. 7 ctc coding obtained by inverting msb (pin 1).
adadc71 rev. c | page 5 of 12 absolute maximum ratings table 2. parameter rating supply voltage 18 v logic supply voltage 7 v analog ground to digital ground 0.3 v analog inputs (pin 25, pin 24) v s digital input ?0.3 v to v dd + 0.3 v junction temperature 175c storage temperature 150c lead temperature (soldering, 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensit ive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adadc71 rev. c | page 6 of 12 theory of operation the analog continuum is partitioned into 2 16 discrete ranges for 16-bit conversion. all analog values within a given quantum are represented by the same digital code, usually assigned to the nominal midrange value. an inherent quantization uncertainty of 1/2 lsb is associated with the resolution, in addition to the actual conversion errors. 0.016 0.013 0.0195 0.0150 0.0180 0 ?0.0150 ?0.0180 ?0.0195 0.006 0.003 0 ?0.003 ?0.006 ?0.016 ?0.013 02 5 7 0 03537-002 temperature ( c) linearity error (% fsr) adadc71 3ppm/ c, 0.006%, @ 25 c figure 2. linearity error vs. temperature 0.100 0.038 ?0.038 0 ?0.068 0.068 0 ?0.100 0 60 50 40 30 20 10 03537-003 temperature ( c) gain drift error (% fsr) 7 0 15ppm/ c figure 3. gain drift error vs. temperature the actual conversion errors associated with adcs are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, reference error, and power supply rejection. the matching and tracking errors in the converter have been minimized by the use of monolithic dacs that include the scaling network. the initial gain and offset errors are specified at 0.2% fsr for gain and 0.1% fsr for offset. these errors may be trimmed to 0 by using external trim circuits as shown in figure 5 and figure 6 . linearity error is defined for unipolar ranges as the deviation from a true straight-line transfer characteristic from a zero voltage analog input, which calls for a zero digital output, to a point that is defined as a full scale. the linearity error is based on the dac resistor ratios. it is unadjustable and is the most meaningful indication of adc accuracy. differential nonlinearity is a measure of the deviation in the staircase step width between codes from the ideal least significant bit step size ( figure 4 ). 03537-004 000 ... 000 all bits on gain error offset error all bits off ?1/2lsb +1/2lsb 011 ... 111 111 ... 111 digital output (cob code) ?fs analog input 0 +fsr ? 1lsb figure 4. transfer characteristics for an ideal bipolar adc monotonic behavior requires that the differential linearity error be less than 1 lsb. however, a monotonic converter can have missing codes. the adadc71 is specified as having no missing codes over temperature ranges noted in the specifications section. there are three types of drift error over temperature: offset, gain and linearity. offset drift causes a shift of the transfer characteristic left or right on the diagram over the operating temperature range. gain drift causes a rotation of the transfer characteristic about the zero point for unipolar ranges or the negative full-scale point for bipolar ranges. the worst case accuracy drift is the summation of all three drift errors over temperature. statistically, however, the drift error behaves as the root-sum-square (rss) and can be shown as 222 l og rss ++= where: )./( cppmerrordriftgain g = )./ ( cfsrofppmerrordriftoffset o = )./ ( cfsrofppmerror linearity l =
adadc71 rev. c | page 7 of 12 description of operation on receipt of a convert start command, the adadc71 converts the voltage at its analog input into an equivalent 16-bit binary number. this conversion is accomplished as follows: the 16-bit successive-approximation register (sar) has its 16-bit outputs connected both to the device bit output pins and to the corresponding bit inputs of the feedback dac. the analog input is successively compared to the feedback dac output, one bit at a time (msb first, lsb last). the decision to keep or reject each bit is then made at the completion of each bit comparison period, depending on the state of the comparator at that time. gain adjustment the gain adjustment circuit consists of a 100 ppm/ o c poten- tiometer connected across v s with its slider connected through a 510 k resistor to pin 29 (gain adjust), as shown in figure 5 . if no external trim adjustment is desired, pin 27 (comparator in) and pin 29 may be left open. 03537-005 adadc71 29 0.01 f 270k +15v 10k to 100k 100ppm/ c ?15v figure 5. gain adjustment circuit zero offset adjustment the zero offset adjustment circuit consists of a 100 ppm/ o c potentiometer connected across v s with its slider connected through a 1.8 m resistor to pin 27 for all ranges. as shown in figure 6, the tolerance of this fixed resistor is not critical; a carbon composition type is generally adequate. using a carbon composition resistor with a ?1200 ppm/ o c temperature coefficient contributes a worst-case offset temperature coefficient of 32 lsb b 14 61 ppm/ lsb 14 1200 ppm/ c = 2.3 ppm/ c of fsr, if the offset adjustment potentiometer is set at either end of its adjustment range. since the maximum offset adjustment required is typically no more than 16 lsb o o 14 , use of a carbon composition offset summing resistor typically contributes no more than 1 ppm/ c of fsr offset temperature coefficient. o 03537-006 adadc71 27 1.8m +15v 10k to 100k ?15v figure 6. zero offset adjustment circuit an alternate offset adjustment circuit, which contributes negligible offset temperature coefficient if metal film resistors (temperature coefficient < 100 ppm/ o c) are used, is shown in figure 7 . in either adjustment circuit, the fixed resistor connected to pin 27 should be located close to this pin to keep the pin connection runs short. pin 27 is quite sensitive to external noise pick-up. 03537-007 adadc71 27 22k m.f. 180k m.f. 180k m.f. +15v 10k to 100k offset adj ?15v figure 7. low temperature coefficient zero adjustment circuit timing the timing diagram is shown in figure 8. receipt of a convert start signal sets the status flag, indicating conversion in progress. this in turn removes the inhibit applied to the gated clock, permitting it to run through 17 cycles. all the sar parallel bits, status flip-flops, and the gated clock inhibit signal are initialized on the trailing edge of the convert start signal. at time t 0 , b 1 is reset and b 2 to b 16 are set unconditionally. at t 1 the bit 1 decision is made (keep) and bit 2 is reset unconditionally. this sequence continues until the bit 16 (lsb) decision (keep) is made at t 16 . the status flag is reset, indicating that the conversion is complete and that the parallel output data is valid. resetting the status flag restores the gated clock inhibit signal, forcing the clock output to the low logic 0 state. note that the clock remains low until the next conversion. corresponding parallel data bits become valid on the same positive-going clock edge. 03537-008 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 (4) (3) (1) 01 1 0 01 1 1 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 0 msb status internal clock convert start bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 lsb lsb msb maximum throughput time conversion time (2) notes: 1. the convert start pulsewidth is 50ns min and must remain low during a conversion. the conversion is initiated by the trailing edge of the convert command. 2. 50 s for 14 bits and 45 s for 13 bits (max). 2. msb decision. 3. clock remains low after last bit decision. figure 8. timing diagram (binary code 0110011101111010)
adadc71 rev. c | page 8 of 12 digital output data parallel data from ttl storage registers is in negative true form (logic 1 = 0 v and logic 0 = 2.4 v). parallel data output coding is complementary binary for unipolar ranges and comple- mentary offset binary for bipolar ranges. parallel data becomes valid at least 20 ns before the status flag returns to logic 0, permitting parallel data transfer to be clocked on the 1 to 0 transition of the status flag (see figure 9 ). parallel data outputs change state on positive-going clock edges. 03537-009 bit 16 valid busy (status) 20ns min to 90ns figure 9. lsb valid to status low short cycle input pin 32 (short cycle) permits the timing cycle shown in figure 8 to be terminated after any number of desired bits has been converted, allowing somewhat shorter conversion times in applications not requiring full 16-bit resolution. when 10-bit resolution is desired, pin 32 is connected to bit 11 output pin 11. the conversion cycle then terminates and the status flag resets after the bit 10 decision (t 10 + 40 ns in the timing diagram of figure 8). short cycle connections and associated maximum 8-, 10-, 12-, 13-, 14-, and 15-bit conversion times are summarized in tabl e 3 . table 3. short cycle connections resolution connect short cycle pin 32 to bits % fsr maximum conversion time status flag reset n/c (open) 16 0.0015 57.0 t 16 + 40 ns pin 16 15 0.003 53.5 t 15 + 40 ns pin 15 14 0.006 50.0 t 14 + 40 ns pin 14 13 0.012 46.5 t 13 + 40 ns pin 13 12 0.024 42.8 t 12 + 40 ns pin 11 10 0.100 35.6 t 10 + 40 ns pin 9 8 0.390 28.5 t 8 + 40 ns input scaling the adadc71 inputs should be scaled as close to the maximum input signal range as possible in order to utilize the maximum signal resolution of the adc. connect the input signal as shown in table 4 . see figure 10 for circuit details. 03537-010 22 analog common 26 bipolar offset comp in 24 25 27 7.5k r2 3.75k 10v span 20v span r1 3.75k from dac comparator to sar v ref figure 10. adadc71 input scaling circuit table 4. input scaling connections input signal line output code conne ct pin 26 to connect pin 24 to for direct input, connect input signal to 10 v cob pin 27 1 input signal pin 24 5 v cob pin 27 1 open pin 25 2.5 v cob pin 27 1 pin 27 1 pin 25 0 v to +5 v csb pin 22 pin 27 1 pin 25 0 v to +10 v csb pin 22 open pin 25 0 v to +20 v csb pin 22 input signal pin 24 1 pin 27 is extremely sensitive to noise and should be guarded by analog common table 5. transition valu es vs. calibration codes output code msb lsb 1 range 10 v 5 v 2.5 v 0 v to +10 v 0 v to +5 v 000. . . .000 2 +full scale +10 v +5 v +2.5 v +10 v +5 v ?3/2 lsb ?3/2 lsb ?3/2 lsb ?3/2 lsb ?3/2 lsb 011 . . . 111 mid scale 0 0 0 +5 v +2.5 v ?1/2 lsb ?1/2 lsb ?1/2 lsb ?1/2 lsb ?1/2 lsb 111 . . . 110 ?full scale ?10 v ?5 v ?2.5 v 0 v 0 v +1/2 lsb +1/2 lsb +1/2 lsb +1/2 lsb +1/2 lsb 1 for lsb value for range and resolution used, see ta ble 6. 2 voltages given are the nominal value for transition to the code specified.
adadc71 rev. c | page 9 of 12 table 6. input voltage range and lsb values analog input voltage range 10 v 5 v 2.5 v 0 v to +10 v 0 v to +5 v code designation cob 1 or ctc 2 cob 1 or ctc 2 cob 1 or ctc 2 csb 3 csb 3 one least significant bit (lsb) n fsr n n n n n n = 8 78.13 mv 39.06 mv 19.53 mv 39.06 mv 19.53 mv n = 10 19.53 mv 9.77 mv 4.88 mv 9.77 mv 4.88 mv n = 12 4.88 mv 2.44 mv 1.22 mv 2.44 mv 1.22 mv n = 13 2.44 mv 1.22 mv 0.61 mv 1.22 mv 0.61 mv n = 14 1.22 mv 0.61 mv 0.31 mv 0.61 mv 0.31 mv n = 15 0.61 mv 0.31 mv 0.15 mv 0.31 mv 0.15 mv 1 cob = complementary offset binary. 2 ctc = complementary twos complementachieved by using an inve rter to complement the most significant bit to produce (msb). 3 csb = complementary straight binary. 03537-011 ?15v +15v a 16-bit successive appromixation register 16-bit dac ref control 3.75k 3.75k 24 26 19 29 28 22 21 25 e in (0v to +10v) i in keep/ reject 7.5k +15v ?15v zero adj 10k to 100k 27 i os = 1.3ma adadc71 1.8m 1 f +5v + 30 + 1 f + 1 f +15v ?15v gain adj 10k to 100 k 270k 0.01 f note: a nalog ( ) and digital ( ) grounds are not tied internally and must be connected externally . 23 figure 11. analog and power connections for unipolar 0 v to +10 v input range 03537-012 ?15v +15v a 16-bit successive appromixation register 16-bit dac ref control 3.75k 3.75k 24 26 19 29 28 22 21 25 e in (?10v to +10v) i in keep/ reject 7.5k +15v ?15v zero adj 10k to 100k 27 i os = 1.3ma adadc71 1.8m 1 f +5v + 30 + 1 f + 1 f +15v ?15v gain adj 10k to 100 k 270k 0.01 f note: a nalog ( ) and digital ( ) grounds are not tied internally and must be connected externally . 23 figure 12. analog and power connections for bipolar ?10 v to +10 v input range calibration (14-bit resolution examples) external ero adjustment and gain adjustment potentiometers, connected as shown in figure 5 and figure 6 , are used for device calibration. to prevent interaction of these two adjustments, ero is always adjusted first and then gain. zero is adjusted with the analog input near the most negative end of the analog range (0 for unipolar and fs for bipolar input ranges). gain is adjusted with the analog input near the most positive end of the analog range. 0 v to +10 v range et the anaog nt to +1 1 00001 v st ero or gta ott 11111111111110 ero s no arate et anaog nt to +r ? + v st gan or 00000000000001 gta ott oe sae gan s no arate asae araton he set anaog nt to +00000 v gta ott oe sho e 01111111111111 ?10 v to +10 v range et the anaog nt to ? v ast ero or 11111111111110 gta ott oeentar oset nar oe et anaog nt to v ast gan or 00000000000001 gta ott oeentar oset nar oe asae araton he set anaog nt to 000000 v gta ott oeentar oset nar oe sho e 01111111111111 other ranges reresentate gta ong or 0 to +10 v an ?10 v to +10 v ranges s gen aoe ong reatonshs an araton onts or 0 to + v ? v to + v an ? v to + v ranges an e on roortona hang the orresonng oe eaents ste or the 0 to +10 v an ?10 v to +10 v ranges resete as nate n a e ero an sae araton an e aoshe to a reson o aroate 1 sng the stat astent roere esre aoe sng a sa sne or trangar ae otage th the sgna ae to the anaog nt the ott an e e throgh eah o the araton oes o nterest to ore arate eterne the enter or en ont o eah srete antaton ee etae esrton o ths na araton tehne s resente n a/d conversion handbook d seingold analog devies n art capter
adadc71 rev. c | page 10 of 12 grounding, decoup ling, and layout considerations many data-acquisition components have two or more ground pins, which are not connected together within the device. these grounds are usually referred to as the digital common (logic power return), analog common (analog power return), or analog signal ground. these grounds (pin 19 and pin 22) must be tied together at one point as close as possible to the converter. ideally, a single solid analog ground plane under the converter would be desirable. current flows through the wires and etch stripes of the circuit card, and since these paths have resistance and inductance, hundreds of millivolts can be generated between the system analog ground point and the ground pins of the adadc71. separate wide conductor stripe ground returns should be provided for high resolution converters to minimize noise and ir losses from the current flow in the path from the converter to the system ground point. in this way the adadc71 supply currents and other digital logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. each of the adadc71s supply terminals should be capacitively decoupled as close to the adadc71 as possible. a large value, such as 1 f, capacitor in parallel with a 0.1 f capacitor is usually sufficient. analog supplies are to be bypassed to the analog common (analog power return) pin 22 and the logic supply is bypassed to digital common (logic power return) pin 19. the metal cover is internally grounded with respect to the power supplies, grounds and electrical signals. do not externally ground the cover. t/h requirements for high resolution applications the characteristics required for high resolution track-and-hold amplifiers are low feedthrough, low pedestal shifts with changes of input signal or temperature, high linearity, low temperature coefficients, and minimal droop rate. the aperture jitter is a result of noise within the switching network that modulates the phase of the hold command, and is manifested in the variations in the value of the analog input that has been held. the aperture error which results from this jitter is directly related to the dv/dt of the analog input. the t/h amplifier slew rate determines the maximum frequency tracking rate and part of the settling time when sampling pulses and square waves. the feedthrough from input to output while in the hold mode should be less than 1 lsb. the amplitude of 1 lsb of the companion adc for a given input range will vary from 610 v for a 14-bit adc using a 0 v to +10 v input range to 4.88 mv for a 12-bit adc using a 10 v input range. the hold mode droop rate should produce less than 1 lsb of droop in the output during the conversion time of the adc. for 610 v/lsb, as noted in the example above, for a 50 s 14-bit adc, the maximum droop rate is 610 v/50 s or 12 v/s during the 50 s conversion period. minimal thermal tail effects are another requirement of high resolution applications. the self-heating errors induced by the changing current levels in the output stages of t/h amps may cause more than 1 lsb of error due to thermal tail effects. the linearity error should be less than 1 lsb over the transfer function, as set by the resolution of the adc. the t/h acquisition time and t/h settling time along with the conversion time of the adc determines the highest sampling rate. this in turn determines the highest input signal frequency that can be sampled at twice a cycle. the maximum input frequency is constrained by the nyquist sampling theorem to be half of the maximum throughput rate. input frequencies higher than half the maximum throughput rate result in under sampling or aliasing errors of the input signal. the pedestal shift due to input signal changes should either be linear, to be seen as a gain error, or negligible, as with the feedthrough specification. the temperature coefficients for drift would be low enough such that full accuracy is maintained over some minimum temperature range. the droop rate and pedestal shift increases above +70 o c (+158 o f). for commercial and industrial users, these shifts only appear above the highest temperatures their equipment might expect to experience. most precision instrumentation is installed only in human inhabitable work spaces or in controlled enclosures if the area has a hostile environment. thus, the adadc71 used with a sample-and-hold amplifier offers high accuracy sampling in high precision applications.
adadc71 rev. c | page 11 of 12 using the adadc71 at slower conversion times the user may wish to run the adadc71 at slower conversion times in order to synchronize the adc with an external clock. this is accomplished by running a slower clock that the internal clock into the start convert input. this clock must consist of narrow negative-going clock pulses, as seen in figure 13 . the pulse must be a minimum of 100 ns wide, but not greater than 700 ns. having a raising edge immediately after a falling edge inhibits the internal clock pulse. this enables the adadc71 to function normally and complete a conversion after 16 clock pulses. the status command functions normally and switches high after the first clock pulse and falls low after the 17 th clock pulse. in this way an external clock can be used to control the adadc71 at slower conversion times. 03537-013 start convert (external clock) clock out status 100ns min 1500ns max 1 t 1 t 15 t 16 t 0 note: 1 extenal clk rate ctrl (pin 23) grounded. figure 13. timing diagram for use with an external clock
adadc71 rev. c | page 12 of 12 outline dimensions notes: 1. index area is indicated by a notch or lead one identification mark located adjacent to lead one. 2. controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.023 (0.58) 0.014 (0.36) 0.910 (23.11) 0.890 (22.61) 1 16 17 32 1.728 (43.89) max 0.225 (5.72) max 0.025 (0.64) 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) 1.102 (27.99) 1.079 (27.41) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.120 (3.05) max pin 1 indicator (note 1) 0.192 (4.88) 0.152 (3.86) 0.206 (5.23) 0.186 (4.72) 0.025 (0.64) min figure 14. 32-lead bottom-brazed ceramic dip for hybrid [bbdip_h] (dh-32e) dimensions shown in inches and (millimeters) ordering guide model linearity error (max) specif ication temp range package option ad adc71jd 0.006% of fsr 0c to +70c ceramic (dh-32e) ad adc71kd 0.003% of fsr 0c to +70c ceramic (dh-32e) ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c03537C0C6/05(c)

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